`timescale 1ns/1ns
module TOP_tb (
    
);


reg clk,rst_n;
// wire in;
wire [1:0] HDB3code;
wire out,random_tp;

initial begin
    clk = 0;
    rst_n = 1;
    #5 rst_n = 0;
    #10 rst_n = 1;
end

always #5 clk = ~clk;

TOP TOP_tb (
    .clk(clk),
    .rst_n(rst_n),
    .random_tp(random_tp),
    .out(out),
    .HDB3code(HDB3code)
);

endmodule //HDB3_decoder_tb